1. Field of the Invention
The present invention relates to a data communication system in which a plurality of nodes are connected through a high performance serial bus carrying isochronous and asynchronous data packets. Such a high performance serial bus is based on the IEEE 1394 Standard, or the like. The isochronous data packets comprise digital audio or video data, or other suitable data.
2. Description of the Related Art
In the P1394 Standard for a High Performance Serial Bus, P1394 Draft 8.0v3, Oct. 16, 1995, pages 30-31, 151-152, 154, 161-163, 345-357, isochronous and asynchronous data communication is described. On pages 30, 31, 151-152, 154, and 163, message formats of isochronous and asynchronous messages are described. In annex J, on pages 345-357, an interface specification is given for internally interfacing a physical layer interface circuit to a link layer interface. In data communication systems in accordance with the IEEE 1394 Standard, through a port the physical layer interface is externally connected to a cable. The cable carries high speed isochronous data, typically digital audio or video data or other high speed data that has to be serviced in real time, and further asynchronous data that are less critical, such a remote control data from one audio or video device to another audio or video device. Examples of such audio and video devices are television sets, TV/VCR combo devices, cameras, DVDs, set-top boxes, camcorders, or the like. The physical layer interface control the timing of the link layer interface. Through configuration of the link layer interface, an isochronous data rate is set, typically rates of 100 Mbit/s, 200 Mbit/s, 400 Mbit/s, or even higher rates. For a 100 Mbit/s rate, data between the physical layer interface and the link layer interface are exchanged on a two bit parallel bus. For 200 Mbit/s and 400 Mbit/s, a four and eight bit parallel bus is applied, respectively. Depending on the driving interface, three or four basic operations are distinguished on the internal parallel bus, determined by a two bit control bus. When the physical layer interface is driving, the operations are idle, status, receive, and transmit. When the link layer interface is driving, the operations are idle, hold, and transmit. Respective operations are requested through transmission of requests on a serial request line between the physical layer interface and the link layer interface, such requests including a type of the request, the speed, a read or write. Request types include immediate control of the internal bus, or, as used for isochronous data transfer, arbitration. On page 353, a register map is described, including an address register for identifying a node of a data communication system in which the physical layer interface is included. A clock signal generated by the physical layer interface controls the timing of the isochronous data streams, such a timing typically being a period of 125 xcexcsec. A combination of a physical and link layer interface is usually implemented in a node of the system, as a chip set of two chips. Herewith, a physical device that is externally connected to the link can transmit and receive high speed isochronous data streams to and from the high perfomance serial bus, data streams of different devices being serviced on a time sharing or time division multiplex basis.
In the Philips Data Sheet, xe2x80x9cPDI1394P11A 3-port physical layer interfacexe2x80x9d, Mar. 10, 1999, a 3-port physical layer interface chip for IEEE 1394-1395 systems is described. On page 4, interfacing is shown with a link layer interface as described in the Philips Data Sheet xe2x80x9cPDI1394L21 1394 full duplex AV link layer controllerxe2x80x9d, Mar. 30, 1999. On page 4 of the PDI1394L21 Data Sheet, coupling of the link layer interface to a two audio/video isochronous transmitter/receivers, and further to a host interface is shown. The host interface can be coupled to an external processor for configuring the interfaces.
In the PHY/LINK Interface as disclosed in the IEEE 1394, as well as in the PHY/LINK Interface as shown in said Philips"" Data Sheets, servicing of isochronous data streams is limited. In a simple configuration as in according to the IEEE 1394 Standard, only a half-duplex isochronous communication of a single external source such as an audio or video device can be serviced. In the Philips PHY/LINK/AV Interface, two half-duplex isochronous data streams or one full-duplex isochronous data stream can be serviced at a time. Particularly when using PHY/LINK Interfaces in so-called Bridges bridging local IEEE 1394 sub-systems such a limitation is disadvantageous.
In the SONY Preliminary Data Sheet xe2x80x9cCXD1947Qxe2x80x9d, an IEEE 1394 Link Layer Interface to PCI Bus Interface is disclosed, for coupling a Physical Layer Interface Circuit to a PCI Bus.
In the Handbook, xe2x80x9cA Guide to VHDLxe2x80x9d, S. Mazor et al., Kluwer Academic Publishers, 1993, VHDL, VHSIC Hardware Description Language, Very High Speed Integrated Circuit, is described. VHDL is a tool for chip designers to implement functionality of chips, particularly logic circuitry. Logic functions are described in a High Level Language and through Compilers and Simulators, Logic Structures in Chips are implemented. Herewith, a suitable tool is provided for programming logic circuits such as FPLA, Field Programmable Logic Arrays, without the need to go through very complicated, and virtually unfeasible designs of logic circuits as with simple gate circuits.
In the Texas Instruments Data Manual xe2x80x9cTSB12LV31xe2x80x9d, September 1998, on page 3-2 thereof, an IEEE 1394-1395 Link-Layer Controller with two Isochronous Receive Ports is disclosed, with a programmable Isochronous channel number.
It is an object of the invention to provide, in a node of a data communication system in which a plurality of nodes is coupled through a high performance serial bus structure, a physical layer and link layer interface structure in which many isochronous data streams can be serviced in an economical and flexible way.
It is another object of the invention to provide such a physical layer and link layer structure particularly suitable for implementation in an IEEE 1394 Bridge.
It is still another object of the invention to provide a means for easily configuring such a physical layer and link layer structure, in accordance with a desired distribution of isochronous and asynchronous data streams.
It is still another object of the invention to provide a addressing mechanism for addressing isochronous and synchronous data packets in such a physical layer and link layer interface structure.
In accordance with the invention, a data communication system is provided comprising:
a plurality of nodes;
a serial bus structure for serially exchanging isochronous data and asynchronous data between said nodes;
a physical layer interface circuit comprised in one of said nodes, said physical layer interface circuit comprising an external port coupled to said serial bus structure, an internal parallel data interface, and a control interface;
a plurality of link layer interface circuits comprised in said one node, each of said link layer interfaces comprising a further internal parallel data interface and a further control interface;
a plurality of bi-directional switches, at one side all of said bi-directional switches being coupled to said internal parallel data interface, and at another side each of said bi-directional switches being coupled to a respective one of said further internal parallel data interfaces; and
a logic circuit comprised in said one node, said logic circuit being coupled between said control interface of said physical layer interface circuit and said further control interfaces of said plurality of link layer interfaces, said logic circuit being arranged for selectively routing isochronous data streams and asynchronous data streams from said link layer interface circuits to said physical layer interface circuit and from said physical layer interface circuit to said link layer interface circuits.
Preferably, the link layer interface circuits have external ports for full duplex data communication with external devices such as digital audio and video devices.
Preferably, the link layer interface circuits have configuration registers that are accessible by an external device such as a host controller. With such a host controller the routing of data streams through the node can be very flexibly programmed.
Preferably, the physical layer interface generates a master clock controlling periodic timing of the isochronous and asynchronous data streams.
Preferably, guaranteed periods are reserved for isochronous data traffic, and excess time for asynchronous data traffic is reserved if current isochronous data traffic is less than the reserved guaranteed period, so that data traffic resources are assigned in a flexible way and still priority is given to real time isochronous data traffic.
Preferabbly, within the node, link layer interface circuits are addressed through a globally unique identifier, one of the link layer interfaces being a master link layer interface circuit for external requesters, and the other link layer interface circuits being slaves, so that the external requesters can easily address the link layer interface circuits.
Preferable, the master link layer interface stores copies of configuration registers of the slaves at offset values so as to allow requesters to access a particular link layer interface circuit.
Preferably, asynchronous packets are provided with a unique label so as to allow external devices to access particular link layer interface circuits.